1. Field of the Invention
The present invention relates to a receiving apparatus such as a pager capable of correctly receiving and reproducing a signal transmitted from a base station modulated by the quadrature frequency shift keying (FSK) system and a decoder capable of correctly reproducing data from such a quadrature FSK modulated signal.
2. Description of the Related Art
First, an explanation will be made of the method of data reception of a pager or other receiving apparatus which receives a quadrature FSK modulated signal and decodes the transferred data. Note that, here, the explanation will be made by taking as an example a receiving apparatus based on the comparator system.
Such a receiving apparatus first receives an FM-modulated signal transmitted from the base station, demodulates it to obtain an analog waveform as shown in FIG. 1A, and compares signals detected corresponding to different carrier frequencies by a comparator to obtain a comparator output signal as shown in FIG. 1B.
It then inputs this comparator output signal to a decoder 10 as shown in FIG. 2 so as to decode the contained data.
The decoder 10 shown in FIG. 2 samples the comparator output signal shown in FIG. 1B at a frequency of a predetermined multiple (x multiple) of the data reception rate and sequentially inputs the obtained bits of the sampling to a shift register. When x-1 number of bits of the sampling are stored in the shift register 1, a data discrimination unit 2 makes a majority decision from the stored bits of the sampling to decide what the bit of the transferred data is.
More specifically, when the comparator output signal is sampled by for example a sampling frequency 16 times the data reception rate, the number of "0"s of the stored bits of the sampling and the number of "1"s of the stored bits of the sampling are compared at a point of time when 15 bits of the sampling are stored in the shift register. When the number of "1" bits of the sampling is eight or more, the bit of the transferred data is decided to be "1", while when the number of "1" bits of the sampling is seven or less, the bit of the transferred data is decided to be "0".
After such a decision is made with respect to one bit of the transferred data, the same processing is immediately repeated with respect to the next bit of the transferred data so as to successively receive the transferred data.
In such a receiving apparatus, however, there are disadvantages that there is a possibility of erroneous reproduction of data and the reliability is not sufficient.
As shown in FIGS. 1A and 1B, there is no disadvantage when the demodulated waveform is theoretical, that is, "clean", but the signal demodulated from the signal which is actually received at the receiving apparatus is "dirty" as shown in FIG. 3A. When there is a succession of "0" bits of data for example, as shown in FIG. 3A, that is, when the bits of the quadrature FSK modulated data change from "00" to "10" or from "10" to "00", the demodulated waveform ends up passing through a region of "1" for a certain extent of time, so there is a disadvantage that the data of one part of the output of the comparator is different. Namely, as indicated by the hatching in FIG. 3B, the bit which originally must be "0" ends up becoming "1". The part of this hatching becomes narrower or wider according to the inclination of the waveform.
When it is desired to reproduce the data shown in FIG. 3B by the decoder of the related art comprising a circuit configuration as shown in FIG. 2, there is a possibility that erroneous data will be reproduced, particularly in a case where the part of the hatching of FIG. 3B becomes wider.
In order to make this part narrower, the value of the threshold value may be changed, but there also exists a possibility that the data of the comparator output per se will become different.
Further, where noise is contained in the data, there is a possibility that the data will be erroneously reproduced due to the noise.